Learn to build OVM & UVM Testbenches from scratch
LEARN AND START BUILDING VERIFICATION TESTBENCHES IN SYSTEM-VERILOG BASED VERIFICATION METHODOLOGIES - OVM AND UVMM
Course content:
Section 1: Introduction and Welcome
Section 2: Fundamentals of OVM/UVM - Transaction Level Modelling
Section 3: Building Testbench Components
Section 4: Sequence based stimulus generation
Section 5: Dynamic Construction and Configurations
Section 6: Assignment- Building and Stimulating APB(Advanced Peripheral Bus) Testbench
Section 7: Summary and Preview of Advanced Topics for Further Study
Description:
The Verification industry is adopting SystemVerilog based UVM Methodology at a rapid pace for most of the current ASIC/SOC Designs and is considered as a key skill for any job in the front end VLSI design/verification jobs.
This course teaches
- Basic concepts of two (similar) methodologies - OVM and UVM -
- Coding and building actual testbenches based on UVM from grounds up.
- Plenty of examples along with assignments (all examples uses UVM)
- Quizzes and Discussion forums
- Hands on assignment to build a complete UVM Verification environent for a most popular SOC Bus protocol - APB Bus
This course is for:
- Verification engineers who have basic understanding of SystemVerilog but new to OVM/UVM methodology
- Students passing out of VLSI/DigitalDesign/Microelectronics looking for a job in front end of VLSI design
- Any VLSI front end design/verification engineer who wants to increase their job opportunities and skills
Requirements:
- Basic understanding of Functional Verification concepts
- Basic understanding of SystemVerilog and object oriented concepts
- Motivation to learn and discuss questions in the Forums
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